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Comment by tubs | original | RISC-V is now officially supported by CPython
[−]tubs · 2026-08-30 Sun 07:59 UTC · link
For AP cores where Python actually runs it’s just “arm8” and pick your incremental version on top.
[−]mort96 · 2026-08-30 Sun 08:53 UTC · link
If you'd limit yourself to cores implementing the Application profile of ARM (Armv8-A etc), you'd do the same and limit yourself to cores implementing the Application profile of RISC-V (RVA23 etc). In that case, you can assume vector instructions and everything else.

If you don't, you get the exact same kind of question with ARM as with RISC-V. Do you use NEON or with SVE? Or do you conservatively compile without vector instructions at all even though it could possibly result in speed-ups for some loops?

[−]shash · 2026-08-30 Sun 09:50 UTC · link
For RISC-V that would functionally be RV64GC then. And you go incrementally from there as required.
[−]ac29 · 2026-08-30 Sun 15:58 UTC · link
Micropython runs on tons of stuff and while it isnt capital-P Python, its close enough for doing a wide variety of embedded work without learning a new language/libraries/etc.